The present invention concerns a hardware implementation which handles positive and negative overflow resulting from arithmetic operations.
When performing arithmetic operations in a computing system positive overflow or negative overflow can occur. For example, when two n-bit integers are added by an arithmetic logic unit (ALU), n+1 bits of result are produced: an n-bit sum and a 1 bit carry-out. For operations using unsigned addition, when the carry-out is zero, then the sum gives the entire result. However, if the carry-out is 1, then "overflow" has occurred because representation of the result requires n+1 bits rather than n bits. For signed numbers, if the two operands have the same sign and the result has a different sign, then overflow has occurred. In the prior art, overflow has typically been handled by a trap to a software exception handler.
When overflow is rare, but must be detected, using a software trap handler is an acceptable practice. However when frequent overflows occur, the use of software traps to handle overflow can have a detrimental effect on system performance. In this case, rather than using a software trap, additional in-line software instructions may be added to the code after each arithmetic instruction. The additional software instructions check for overflow and, when present, adjusts the result or re-executes the code with more bits of precision.
In applications where overflow never occurs, then software trapping can be disabled and there is no requirement for in-line software checking for overflows. However, when positive and/or negative overflows are fairly frequent it is desirable to have a method of handling these overflows in an efficient manner without using software traps or additional in-line code.